HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 140

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.2.2
The user break address mask register (UBAMR) consists of two registers: user break address mask
register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit
readable/writable registers. UBAMRH specifies whether to mask any of the break address bits set
in UBARH, and UBAMRL specifies whether to mask any of the break address bits set in UBARL.
• UBAMRH Bits 15 to 0: specifies user break address mask 31 to 16 (UBM31 to UBM16)
• UBAMRL Bits 15 to 0: specifies user break address mask 15 to 0 (UBM15 to UBM0)
7.2.3
The user break bus cycle register (UBBR) is a 16-bit readable/writable register that sets the four
break conditions.
Rev. 2.00, 09/04, page 98 of 720
Bit
15 to 8 
7
6
Bit
UBAMRH15 to
UBAMRH 0
UBAMRL15 to
UBAMRL0
Bit Name
CP1
CP0
User Break Address Mask Register (UBAMR)
User Break Bus Cycle Register (UBBR)
Bit Name
UBM31 to
UBM16
UBM15 to
UBM0
Initial
Value
All 0
0
0
Initial
Value
All 0
All 0
R/W
R
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
CPU Cycle/DTC Cycle Select 1 and 0
These bits specify break conditions for CPU cycles or
DTC cycles.
00: No user break interrupt occurs
01: Break on CPU cycles
10: Break on DTC cycles
11: Break on both CPU and DTC cycles
Description
User Break Address Mask 31 to 16
0: Corresponding UBA bit is included in the
1: Corresponding UBA bit is not included in
User Break Address Mask 15 to 0
0: Corresponding UBA bit is included in the
1: Corresponding UBA bit is not included in
break conditions
the break conditions
break conditions
the break conditions