HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 455

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.3.1
MCR is a 16-bit register that controls the HCAN2 operation.
Bit
15
14
13
Bit Name
TST7
TST6
TST5
Master Control Register (MCR)
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Test Mode
Enables/disables the test modes settable by TST[6:0].
When this bit is set, the following TST[6:0] become
effective.
0: HCAN2 is in normal mode
1: HCAN2 is in test mode
Write CAN Error Counters
Enables the TEC (Transmit Error Counter) and REC
(Receive Error Counter) to be writable. The same value
can only be written into the TEC/REC at the same time.
The maximum value that can be written into the TEC/REC
is D'255 (H'FF). This means that the HCAN2 cannot be
forced into the bus off state. Before writing into the
TEC/REC, HCAN2 needs to be put into Halt Mode, and
when writing into the TEC/REC, the TST7 (MCR15) needs
to be ‘1’. Only the same value can be set between
TEC/REC, and the value written into TEC is used to write
REC.
0: TEC/REC is not writable but read-only
1: TEC/REC is writable with the same value at the same
Force to Error Passive
Forces HCAN2 to become error passive. When this bit is
set, HCAN2 behaves as an error passive node, regardless
of the error counters.
0: State of HCAN2 depends on the error counters
1: HCAN2 behaves as an error passive node regardless of
time
the error counters
Rev. 2.00, 09/04, page 413 of 720