HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 68

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.4.3
The instruction formats and the meaning of source and destination operand are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Rev. 2.00, 09/04, page 26 of 720
Addressing
Mode
PC relative
addressing
Immediate
addressing
Instruction Format
Instruction
Format
Rn
#imm:8
#imm:8
#imm:8
Effective Address Calculation
The effective address is the sum of the register PC
and Rn.
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and then quadrupled.
PC
Rn
+
PC + Rn
Equation
PC + Rn


