HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 625

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.2
Table 22.1 shows the H-UDI pin configuration.
Table 22.1 H-UDI Pins
22.3
The H-UDI has the following registers. For the register addresses and register states in each
operating mode, refer to appendix A, Internal I/O Register.
• Instruction register (SDIR)
• Status register (SDSR)
• Data register H (SDDRH)
• Data register L (SDDRL)
• Bypass register (SDBPR)
Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by
serial transfer from the test data input pin (TDI). Data from the status register (SDSR), and SDDR
can be output via the test data output pin (TDO). The bypass register (SDBPR) is a one-bit register
Pin Name
Test clock
Test mode
select
Test data
input
Test data
output
Test reset
Input/Output Pins
Register Description
Abbreviation
TCK
TMS
TDI
TDO
TRST
I/O
Input
Input
Input
Output
Input
Function
Test clock input
TCK supplies an independent clock to the H-UDI. As
the clock input to TCK is supplied directly to the H-UDI,
a clock waveform with a duty cycle close to 50%
should be input (see section 25, Electrical
Characteristics, for details).
Test mode select input signal
TMS is sampled at the rising edge of TCK. TMS
controls the internal state of the TAP controller.
Serial data input
TDI performs serial input of instructions and data to H-
UDI registers. TDI is sampled at the rising edge of
TCK.
Serial data output
TDO performs serial output of instructions and data
from H-UDI registers. Transfer is synchronized with
TCK. When no signal is being output, TDO goes to the
high-impedance state.
Test reset input signal
TRST is used to initialize the H-UDI asynchronously.
Rev. 2.00, 09/04, page 583 of 720