HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 21

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4 Operation .......................................................................................................................... 491
16.5 Interrupts........................................................................................................................... 500
16.6 Operation Timing.............................................................................................................. 501
16.7 Usage Notes ...................................................................................................................... 505
16.8 Port Output Enable (POE)................................................................................................. 508
Section 17 Pin Function Controller (PFC).........................................................515
17.1 Register Descriptions ........................................................................................................ 525
17.2 Precautions for Use ........................................................................................................... 536
Section 18 I/O Ports ...........................................................................................537
18.1 Port A................................................................................................................................ 537
18.2 Port B ................................................................................................................................ 539
16.3.4 Timer Counter (MMT_TCNT) ............................................................................ 490
16.3.5 Timer Buffer Registers (TBR) ............................................................................. 490
16.3.6 Timer General Registers (TGR)........................................................................... 490
16.3.7 Timer Dead Time Counters (TDCNT)................................................................. 490
16.3.8 Timer Dead Time Data Register (MMT_TDDR) ................................................ 490
16.3.9 Timer Period Buffer Register (TPBR) ................................................................. 490
16.3.10 Timer Period Data Register (TPDR).................................................................... 491
16.4.1 Sample Setting Procedure .................................................................................... 492
16.4.2 Output Protection Functions ................................................................................ 500
16.6.1 Input/Output Timing ............................................................................................ 501
16.6.2 Interrupt Signal Timing........................................................................................ 504
16.7.1 Module Standby Mode Setting ............................................................................ 505
16.7.2 Notes for MMT Operation ................................................................................... 505
16.8.1 Features................................................................................................................ 508
16.8.2 Input/Output Pins................................................................................................. 509
16.8.3 Register Descriptions........................................................................................... 509
16.8.4 Operation ............................................................................................................. 512
16.8.5 Usage Note........................................................................................................... 513
17.1.1 Port A I/O Register L (PAIORL)......................................................................... 525
17.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1)................................. 525
17.1.3 Port B I/O Register (PBIOR) ............................................................................... 529
17.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2)...................................... 529
17.1.5 Port D I/O Register L (PDIORL)......................................................................... 530
17.1.6 Port D Control Registers L1 and L2 (PDCRL1 and PDCRL2) ........................... 531
17.1.7 Port E I/O Registers L and H (PEIORL and PEIORH)........................................ 532
17.1.8 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) ....... 533
18.1.1 Register Descriptions........................................................................................... 538
18.1.2 Port A Data Register L (PADRL) ........................................................................ 538
18.2.1 Register Descriptions........................................................................................... 539
18.2.2 Port B Data Register (PBDR) .............................................................................. 539
Rev. 2.00, 09/04, page xix of xl