HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 272

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3. Initialization
Table 10.41 Registers and Counters Requiring Initialization
Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and
4. PWM Output Level Setting
5. Dead Time Setting
Rev. 2.00, 09/04, page 230 of 720
Register/Counter
TGRC_3
TDDR
TCBR
TGRD_3, TGRC_4, TGRD_4
TCNT_4
In complementary PWM mode, there are six registers that must be initialized.
Before setting complementary PWM mode with bits MD3–MD0 in the timer mode register
(TMDR), the following initial register values must be set.
TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM
carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer
register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier
cycle. Set dead time Td in the timer dead time data register (TDDR).
Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and
TGRD_4.
The values set in the five buffer registers excluding TDDR are transferred simultaneously to
the corresponding compare registers when complementary PWM mode is set.
Set TCNT_4 to H'0000 before setting complementary PWM mode.
In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP
in the timer output control register (TOCR).
The output level can be set for each of the three positive phases and three negative phases of 6-
phase output.
Complementary PWM mode should be cleared before setting or changing output levels.
In complementary PWM mode, PWM pulses are output with a non-overlapping relationship
between the positive and negative phases. This non-overlap time is called the dead time.
The non-overlap time is set in the timer dead time data register (TDDR). The value set in
TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3
and TCNT_4. Complementary PWM mode should be cleared before changing the contents of
TDDR.
dead time Td set in TDDR.
Set Value
1/2 PWM carrier cycle + dead time Td
Dead time Td
1/2 PWM carrier cycle
Initial PWM duty value for each phase
H'0000