HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 650

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24.2.2
SYSCR is an 8-bit readable/writable register that performs AUD software reset control and
enables/disables the access to the on-chip RAM.
Rev. 2.00, 09/04, page 608 of 720
Bit
7, 6
5 to 2
1
0
Bit Name


AUDSRST 0
RAME
System Control Register (SYSCR)
Initial
Value
All 1
All 0
1
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 1, and should always be
written with 1.
Reserved
These bits are always read as 0, and should always be
written with 0.
AUD Software Reset
This bit controls the AUD reset by software. When 0 is
written to AUDSRST, AUD module shifts to power-on
reset state.
0: Shifts to AUD reset state.
1: Clears the AUD reset.
RAM Enable
This bit enables/disables the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
When this bit is cleared to 0, the access to the on-chip
RAM is disabled. In this case, an undefined value is
returned when reading or fetching the data or
instruction from the on-chip RAM, and writing to the on-
chip RAM is ignored.
When RAME is cleared to 0 to disable the on-chip
RAM, an instruction to access the on-chip RAM should
not be set next to the instruction to write to SYSCR. If
such an instruction is set, normal access is not
guaranteed.
When RAME is set to 1 to enable the on-chip RAM, an
instruction to read SYSCR should be set next to the
instruction to write to SYSCR. If an instruction to access
the on-chip RAM is set next to the instruction to write to
SYSCR, normal access is not guaranteed.