HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 22

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.3 Port D................................................................................................................................ 541
18.4 Port E ................................................................................................................................ 543
18.5 Port F ................................................................................................................................ 546
Section 19 Flash Memory (F-ZTAT Version)................................................... 549
19.1 Features............................................................................................................................. 549
19.2 Mode Transitions .............................................................................................................. 550
19.3 Block Configuration ......................................................................................................... 554
19.4 Input/Output Pins.............................................................................................................. 555
19.5 Register Descriptions........................................................................................................ 555
19.6 On-Board Programming Modes........................................................................................ 559
19.7 Flash Memory Emulation in RAM ................................................................................... 563
19.8 Flash Memory Programming/Erasing............................................................................... 565
19.9 Program/Erase Protection ................................................................................................. 569
19.10 PROM Programmer Mode................................................................................................ 571
19.11 Notes on Use..................................................................................................................... 571
19.12 Notes when Converting the F-ZTAT Versions to the Mask-ROM Versions.................... 571
19.13 Notes on Flash Memory Programming and Erasing ......................................................... 571
Section 20 Mask ROM ...................................................................................... 577
20.1 Notes on Use..................................................................................................................... 577
Section 21 RAM ................................................................................................ 579
21.1 Usage Note........................................................................................................................ 579
Rev. 2.00, 09/04, page xx of xl
18.3.1 Register Descriptions........................................................................................... 541
18.3.2 Port D Data Register L (PDDRL)........................................................................ 541
18.4.1 Register Descriptions........................................................................................... 544
18.4.2 Port E Data Registers H and L (PEDRH and PEDRL) ........................................ 544
18.5.1 Register Descriptions........................................................................................... 546
18.5.2 Port F Data Register (PFDR) ............................................................................... 546
19.5.1 Flash Memory Control Register 1 (FLMCR1) .................................................... 555
19.5.2 Flash Memory Control Register 2 (FLMCR2) .................................................... 557
19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 557
19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 558
19.5.5 RAM Emulation Register (RAMER)................................................................... 558
19.6.1 Boot Mode ........................................................................................................... 560
19.6.2 Programming/Erasing in User Program Mode..................................................... 562
19.8.1 Program/Program-Verify Mode........................................................................... 565
19.8.2 Erase/Erase-Verify Mode .................................................................................... 567
19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 567
19.9.1 Hardware Protection ............................................................................................ 569
19.9.2 Software Protection ............................................................................................. 570
19.9.3 Error Protection ................................................................................................... 570