HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 535

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Count Operation: Set 2Td (Td: value set in TDDR) as the initial value of the TCNT counter
when CST bit in TCNR is set to 0.
When the CST bit is set to 1, TCNT counts up to {value set in TPBR + 2Td}, and then starts
counting down. When TCNT reaches 2Td, it starts counting up again, and continues in this way.
TCNT is constantly compared with TGRU, TGRV, and TGRW. In addition, it is compared with
TGRUU, TGRVU, TGRWU, and TPDR when counting up, and with TGRUD, TGRVD,
TGRWD, and 2Td when counting down.
TDCNT0 to TDCNT5 are read-only counters. It is not necessary to set their initial values.
TDCNT0, TDCNT2, and TDCNT4 start counting up at the falling edge of a positive phase
compare match output when TCNT is counting down. When they become equal to TDDR they are
cleared to 0 and halt.
TDCNT1, TDCNT3, and TDCNT5 start counting up at the falling edge of a negative phase
compare match output when TCNT is counting up. When they match TDDR they are cleared to 0
and halt.
TDCNT0 to TDCNT5 are compared with TDDR only while a count operation is in progress. No
count operation is performed when the TDDR value is 0.
Figure 16.3 shows an example of the TCNT count operation.
TGRUU
TGRUD
H'FFFF
H'0000
TGRU
TPDR
2Td
Figure 16.3 Example of TCNT Count Operation
Td
TCNT
Td
Rev. 2.00, 09/04, page 493 of 720
2Td
2Td
1/2 period
(TPBR)
Td