HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 518

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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15.4.7
The HCAN2 halt mode is provided to enable mailbox settings to be changed without performing
an HCAN2 hardware or software reset. In HCAN2 halt mode, the contents of all registers are
retained. Figure 15.14 shows a flowchart of HCAN2 halt mode.
HCAN2 halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN2 halt mode is delayed until
the bus becomes idle.
HCAN2 halt mode is cleared by clearing MCR1 to 0.
Rev. 2.00, 09/04, page 476 of 720
HCAN2 Halt Mode
No
CAN bus communication possible
11 recessive bits received
Figure 15.14 HCAN2 Halt Mode Flowchart
Mailbox setting
GSR4 = 1?
Yes
Yes
Yes
MCR1 = 1
MCR1 = 0
Bus idle?
?
No
No
No
: Settings by user
: Processing by hardware

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