HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 425

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.3.2
ADCSR for each module controls A/D conversion operations.
Note:
Bit
7
6
5
4
3
2
1
0
Bit Name
ADF
ADIE
ADM1
ADM0

CH2
CH1
CH0
*
A/D Control/Status Registers 0, 1 (ADCSR_0, ADCSR_1)
Only 0 can be written to clear the flag.
Initial
Value
0
0
0
0
1
0
0
0
R/W
R/(W)*
R/W
R/W
R/W
R
R/W
R/W
R/W
Description
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
A/D Mode 1 and 0
Select the A/D conversion mode.
00: Single mode
01: 4-channel scan mode
10: 8-channel scan mode
11: Setting prohibited
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
Reserved
This bit is always read as 1, and should only be written
with 1.
Channel Select 2 to 0
Select analog input channels. See table 13.2.
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
When A/D conversion ends in single mode
When A/D conversion ends on all specified channels
in scan mode
When 0 is written after reading ADF = 1
When the DTC is activated by an ADI interrupt and
ADDR is read with the DISEL bit in DTMR of DTC = 0
Rev. 2.00, 09/04, page 383 of 720