HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 654
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HD64F7047F50V
Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Specifications of HD64F7047F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Clearing Software Standby Mode: Software standby mode is cleared by the condition below.
• Clearing by the NMI interrupt input
• Clearing by the RES pin
• Clearing by the IRQ interrupt input
Rev. 2.00, 09/04, page 612 of 720
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in ICR1 of the interrupt controller (INTC)) is detected, clock oscillation is started.
This clock pulse is supplied only to the watchdog timer (WDT).
After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT
before the transition to software standby mode, the WDT overflow occurs. Since this overflow
indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after
this overflow. Software standby mode is thus cleared and the NMI exception handling is
started.
When clearing software standby mode by the NMI interrupt, set CKS2 to CKS0 bits so that the
WDT overflow period will be longer than the oscillation stabilization time.
When software standby mode is cleared by the falling edge of the NMI pin, the NMI pin
should be high when the CPU enters software standby mode (when the clock pulse stops) and
should be low when the CPU returns from standby mode (when the clock is initiated after the
oscillation stabilization). When software standby mode is cleared by the rising edge of the
NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the
clock pulse stops) and should be high when the CPU returns from software standby mode
(when the clock is initiated after the oscillation stabilization).
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation is started, clock pulse is supplied to the entire chip. Ensure that the RES pin is held
low until clock oscillation stabilizes. When the RES pin is driven high, the CPU starts the reset
exception handling.
When the IRQEL bit in the standby control register (SBYCR) is set to 1 and when the falling
edge or rising edge of the IRQ pin (selected by the IRQ3S to IRQ0S bits in ICR1 of the
interrupt controller (INTC) and the IRQ3ES[1:0] to IRQ0ES[1:0] bits in ICR2) is detected,
clock oscillation is started.* This clock pulse is supplied only to the watchdog timer (WDT).
The IRQ interrupt priority level should be higher than the interrupt mask level set in the status
register (SR) of the CPU before the transition to software standby mode.
After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT
before the transition to software standby mode, the WDT overflow occurs. Since this overflow
indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after
this overflow. Software standby mode is thus cleared and the IRQ exception handling is
started.
When clearing software standby mode by the IRQ interrupt, set CKS2 to CKS0 bits so that the
WDT overflow period will be longer than the oscillation stabilization time.
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