HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 103

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.2
5.2.1
Resets have the highest priority of any exception source. There are two types of resets: manual
resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of
the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in
manual resets, they are not.
Table 5.5
5.2.2
Power-On Reset by RES Pin: When the RES pin is driven low, the LSI becomes to be a power-
on reset state. To reliably reset the LSI, the RES pin should be kept at low for at least the duration
of the oscillation settling time when applying power or when in standby mode (when the clock
circuit is halted) or at least 20 t
internal status and all registers of on-chip peripheral modules are initialized. See Appendix B, Pin
States, for the status of individual pins during the power-on reset status.
In the power-on reset status, power-on reset exception processing starts when the RES pin is first
driven low for a set period of time and then returned to high. The CPU will then operate as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
4. The values fetched from the exception processing vector table are set in PC and SP, then the
Be certain to always perform power-on reset processing when turning the system power on.
Type
Power-on reset
Manual reset
exception processing vector table.
of the status register (SR) are set to H'F (B'1111).
program begins executing.
Resets
Types of Reset
Power-On Reset
Reset Status
RES
Low
High
High
Conditions for Transition
to Reset Status
WDT
Overflow MRES

Overflow

cyc
when the clock circuit is running. During power-on reset, CPU

High
Low
CPU/INTC
Initialized
Initialized
Initialized
Rev. 2.00, 09/04, page 61 of 720
Internal Status
On-Chip
Peripheral
Module
Initialized
Initialized
Not initialized Not initialized
PFC, IO Port
Initialized
Not initialized