HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 133

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7
Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception processing starts and fetching of the first instruction of the
interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an
IRQ interrupt is accepted.
Table 6.3
Note:
Item
DTC active judgment
Interrupt priority judgment
and comparison with SR
mask bits
Wait for completion of
sequence currently being
executed by CPU
Time from start of interrupt
exception processing until
fetch of first instruction of
exception service routine
starts
Interrupt
response
time
*
Interrupt Response Time
0.48 µs at 40 MHz is the value in the case that m1 = m2 = m3 = m4 = 1.
m1 to m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Interrupt Response Time
Maximum: 12 + 2 (m1 + m2
Minimum: 10
Total: (7 or 8) + m1 +
NMI, Peripheral
Module
0 or 1
2
X (≥ 0)
5 + m1 + m2 + m3
m2 + m3+X
+ m3) + m4
Number of States
IRQ
1
3
X (≥ 0)
5 + m1 + m2 + m3
9 + m1 + m2 +
m3 + X
12
13 + 2 (m1 + m2
+ m3) + m4
Rev. 2.00, 09/04, page 91 of 720
Remarks
1 state required for
interrupt signals for which
DTC activation is possible
The longest sequence is for
interrupt or address-error
exception processing (X =
4 + m1 + m2 + m3 + m4). If
an interrupt-masking
instruction follows,
however, the time may be
even longer.
Performs the saving PC
and SR, and vector
address fetch.
0.25 0.3 µs at 40 MHz
0.48 µs at 40 MHz*