HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 27

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figures
Section 1 Overview
Figure 1.1 Block Diagram of SH7047 ............................................................................................ 4
Figure 1.2 SH7047 Pin Arrangement.............................................................................................. 5
Section 2 CPU
Figure 2.1 CPU Internal Registers ................................................................................................ 15
Figure 2.2 Data Format in Registers ............................................................................................. 18
Figure 2.3 Data Formats in Memory............................................................................................. 18
Figure 2.4 Transitions between Processing States ........................................................................ 42
Section 3 MCU Operating Modes
Figure 3.1 The Address Map for the Operating Modes of SH7047 Flash Memory Version ........ 48
Figure 3.2 The Address Map for the Operating Modes of SH7049 Mask ROM Version ............ 49
Section 4 Clock Pulse Generator
Figure 4.1 Block Diagram of the Clock Pulse Generator ............................................................. 51
Figure 4.2 Connection of the Crystal Resonator (Example) ......................................................... 52
Figure 4.3 Crystal Resonator Equivalent Circuit .......................................................................... 52
Figure 4.4 Example of External Clock Connection ...................................................................... 53
Figure 4.5 Cautions for Oscillator Circuit System Board Design................................................. 55
Figure 4.6 Recommended External Circuitry Around the PLL .................................................... 56
Section 6 Interrupt Controller (INTC)
Figure 6.1 INTC Block Diagram .................................................................................................. 74
Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control................................................... 83
Figure 6.3 Interrupt Sequence Flowchart...................................................................................... 89
Figure 6.4 Stack after Interrupt Exception Processing.................................................................. 90
Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted ..................... 92
Figure 6.6 Interrupt Control Block Diagram ................................................................................ 93
Section 7 User Break Controller (UBC)
Figure 7.1 User Break Controller Block Diagram ........................................................................ 96
Figure 7.2 Break Condition Determination Method ................................................................... 102
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ............................................................................................. 110
Figure 8.2 Activating Source Control Block Diagram ............................................................... 118
Figure 8.3 DTC Register Information Allocation in Memory Space.......................................... 119
Figure 8.4 Correspondence between DTC Vector Address and Transfer Information............... 119
Figure 8.5 DTC Operation Flowchart......................................................................................... 122
Figure 8.6 Memory Mapping in Normal Mode .......................................................................... 123
Figure 8.7 Memory Mapping in Repeat Mode ........................................................................... 124
Figure 8.8 Memory Mapping in Block Transfer Mode............................................................... 125
Rev. 2.00, 09/04, page xxv of xl