HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 599

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.5.2
FLMCR2 is a register that displays the state of flash memory programming/erasing.
19.5.3
EBR1 specifies the flash memory erase block. EBR1 is initialized to H'00 when a high level is
input to the FWP pin. It is also initialized to H'00, when the SWE bit in FLMCR1 is 0 regardless
of value in the FWP pin. Do not set more than one bit at a time in EBR1 and EBR2, as this will
cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
Bit
7
6 to 0 
Bit
7
6
5
4
3
2
1
0
Bit Name
FLER
Bit Name
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Flash Memory Control Register 2 (FLMCR2)
Erase Block Register 1 (EBR1)
Initial
Value
0
0
0
0
0
0
0
0
Initial
Value
0
All 0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When flash
memory goes to the error-protection state, FLER is set to
1.
See section 19.9.3, Error Protection, for details.
Reserved
These bits are always read as 0.
Description
When this bit is set to 1, 4 kbytes of EB7 (H'007000 to
H'007FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB6 (H'006000 to
H'006FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB5 (H'005000 to
H'005FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB4 (H'004000 to
H'004FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB3 (H'003000 to
H'003FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB2 (H'002000 to
H'002FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB1 (H'001000 to
H'001FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB0 (H'000000 to
H'000FFF) are to be erased.
Rev. 2.00, 09/04, page 557 of 720