HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 121

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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6.3.3
ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins
IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be
withdrawn by writing 0 to IRQnF after reading IRQnF = 1.
Bit
15 to 8
7
6
5
4
3 to 0
IRQ Status Register (ISR)
Bit Name
IRQ0F
IRQ1F
IRQ2F
IRQ3F
Initial
Value
All 0
0
0
0
0
All 0
R/W
R
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
IRQ0 to IRQ3 Flags
These bits display the IRQ0 to IRQ3 interrupt request
status.
[Setting condition]
[Clearing conditions]
Reserved
These bits are always read as 0. The write value
should always be 0.
When interrupt source that is selected by ICR1
and ICR2 has occurred.
When 0 is written after reading IRQnF = 1
When interrupt exception processing has been
executed at high level of IRQn input under the low
level detection mode.
When IRQn interrupt exception processing has
been executed under the edge detection mode of
falling edge, rising edge or both of falling and
rising edge.
When the DISEL bit of DTMR of DTC is 0, after
DTC has been started by IRQn interrupt.
Rev. 2.00, 09/04, page 79 of 720

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