HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 78

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
Rev. 2.00, 09/04, page 36 of 720
Instruction
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
MAC.L
MAC.W
MUL.L
MULS.W
MULU.W
NEG
NEGC
SUB
SUBC
SUBV
*
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
@Rm+,@Rn+ 0000nnnnmmmm1111
@Rm+,@Rn+ 0100nnnnmmmm1111
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
The normal number of execution states is shown. (The number in parentheses is the
number of states when there is contention with the preceding or following instructions.)
Instruction Code
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Operation
Rn – 1 → Rn, when Rn
is 0, 1 → T. When Rn is
nonzero, 0 → T
Byte in Rm is sign-
extended → Rn
Word in Rm is sign-
extended → Rn
Byte in Rm is zero-
extended → Rn
Word in Rm is zero-
extended → Rn
Signed operation of
(Rn) × (Rm) + MAC →
MAC 32 × 32 + 64 →
64 bits
Signed operation of
(Rn) × (Rm) + MAC →
MAC 16 × 16 + 64 →
64 bits
Rn × Rm → MACL,
32 × 32 → 32 bits
Signed operation of
Rn × Rm → MACL 16 ×
16 → 32 bits
Unsigned operation of
Rn × Rm → MACL 16 ×
16 → 32 bits
0 – Rm → Rn
0 – Rm – T → Rn,
Borrow → T
Rn – Rm → Rn
Rn – Rm – T → Rn,
Borrow → T
Rn – Rm → Rn,
Underflow → T
Execution
States
1
1
1
1
1
3/(2 to 4)*
3/(2)*
2 to 4*
1 to 3*
1 to 3*
1
1
1
1
1
T Bit
Comparison
result
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Borrow
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Borrow
Overflow