HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 125

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4.2
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules.
As a different interrupt vector is assigned to each interrupt source, the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers A, D to I, K
(IPRA, IPRD to IPRI, IPRK). On-chip peripheral module interrupt exception processing sets the
interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-
chip peripheral module interrupt that was accepted.
6.4.3
A user break interrupt has a priority of level 15, and occurs when the break condition set in the
user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are
held until accepted. User break interrupt exception processing sets the interrupt mask level bits (I3
to I0) in the status register (SR) to level 15. For more details about the user break interrupt, see
section 7, User Break Controller (UBC).
6.4.4
High-performance user debugging interface (H-UDI) interrupt has a priority level of 15, and
occurs when an H-UDI interrupt instruction is serially input. H-UDI interrupt requests are detected
by edge and are held until accepted. H-UDI exception processing sets the interrupt mask level bits
(I3-I0) in the status register (SR) to level 15. For more details about the H-UDI interrupt, see
section 22, High-Performance User Debug Interface (H-UDI).
IRQ pins
(Acceptance of IRQn interrupt/DTC transfer end/
writing 0 after reading IRQnF = 1)
On-Chip Peripheral Module Interrupts
User Break Interrupt
H-UDI Interrupt
Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control
detection
detection
RESIRQn
Level
Edge
R
S
Q
IRQnS
IRQnES
ISR.IRQnF
Rev. 2.00, 09/04, page 83 of 720
DTC starting request
DTC
CPU interrupt
request