HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 254

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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10.4.6
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT counts up or down accordingly. This mode can be set for channels 1 and 2.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits
CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of
TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs
when TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is
counting up or down.
Table 10.32 shows the correspondence between external clock pins and channels.
Table 10.32 Phase Counting Mode Clock Input Pins
Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the
phase counting mode setting procedure.
Rev. 2.00, 09/04, page 212 of 720
Channels
When channel 1 is set to phase counting mode
When channel 2 is set to phase counting mode
Phase Counting Mode
<Phase counting mode>
Figure 10.24 Example of Phase Counting Mode Setting Procedure
Select phase counting
Phase counting mode
Start count
mode
[1]
[2]
[1] Select phase counting mode with bits
[2] Set the CST bit in TSTR to 1 to start
MD3 to MD0 in TMDR.
the count operation.
A-Phase
TCLKA
TCLKC
External Clock Pins
B-Phase
TCLKB
TCLKD

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