HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 641

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.4.2
The AUD latches the AUDATA input when AUDSYNC is asserted. The following AUDATA
input format should be used.
23.4.3
Operation starts in RAM monitor mode when AUDRST is asserted, AUDMD is driven high, then
AUDRST is negated.
Figure 23.5 shows an example of a read operation, and figure 23.6 an example of a write
operation.
When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address,
or data (writing only) is input in the format shown in figure 23.4, execution of read/write access to
the specified address is started. During internal execution, the AUD returns Not Ready (0000).
When execution is completed, the Ready flag (0001) is returned (figures 23.5 and 23.6). Table
23.2 shows the Ready flag format.
In a read, data of the specified size is output when AUDSYNC is negated following detection of
this flag (figure 23.5).
If a command other than the above is input in DIR, the AUD treats this as a command error,
disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the
command specified in DIR causes a bus error, the AUD disables processing and sets bit 2 in the
Ready flag to 1 (figure 23.7).
Communication Protocol
Operation
Input format
0000
Command
DIR
Figure 23.4 AUDATA Input Format
Spare bits (4 bits): b'0000
A3 to A0
Fixed at 1
Bit 3
Address
. . . . . .
0: Read
1: Write
Bit 2
A31 to A28 D3 to D0
00: Byte
01: Word
10: Longword
Bit 1
Data (in case of write only)
Rev. 2.00, 09/04, page 599 of 720
Bit 0
B write: n = 7
W write: n = 15
L write: n = 31
. . . . . .
Dn to Dn-3