HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 355

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.9.4
Input Level Detection Operation: If the input conditions set by the ICSR1 occur on any of the
POE pins, all high-current pins become high-impedance state. However, only when the general
input/output function or MTU function is selected, the large-current pin is in the high-impedance
state.
1. Falling Edge Detection
2. Low-Level Detection
Pφ
Sampling
clock
POE input
PE9/
TIOC3B
When low level is
sampled at all points
When high level is
sampled at least once
Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C,
When a change from high to low level is input to the POE pins.
Figure 10.115 shows the low-level detection operation. Sixteen continuous low levels are
sampled with the sampling clock established by the ICSR1. If even one high level is detected
during this interval, the low level is not accepted.
Furthermore, the timing when the large-current pins enter the high-impedance state from the
sampling clock is the same in both falling-edge detection and in low-level detection.
PE15/TIOC4D/IRQOUT) also go to the high-impedance state at the same timing.
Operation
1
1
Figure 10.115 Low-Level Detection Operation
8/16/128 clock
cycles
2
2
3
Rev. 2.00, 09/04, page 313 of 720
16
13
Flag not set
High-impedance
state*
Flag set
(POE received)