HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 131

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7047F50V
Manufacturer:
PANJIT
Quantity:
30 000
Part Number:
HD64F7047F50V
Manufacturer:
RENESAS
Quantity:
386
Part Number:
HD64F7047F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7047F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7047F50V
Quantity:
2 070
Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU
Copy accept-interrupt
Branch to exception
execution state
Save SR to stack
Save PC to stack
IRQOUT = high
Read exception
level to I3 to I0
IRQOUT = low
service routine
Interrupt?
vector table
Program
*1 IRQOUT is the same signal as interrupt request signal to the CPU (see figure 6.1).
*2 When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when
NMI?
Yes
Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR.
the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).
However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted
and has output an interrupt request to the CPU, the IRQOUT pin holds low level.
Yes
No
No
User break?
*1
*2
Yes
Figure 6.3 Interrupt Sequence Flowchart
No
interrupt?
H-UDI
Yes
Yes
No
interrupt?
level 14?
Level 15
I3 to I0 ≤
No
Yes
Yes
No
Rev. 2.00, 09/04, page 89 of 720
interrupt?
level 13?
Level 14
I3 to I0 ≤
No
Yes
Yes
No
interrupt?
I3 to I0 =
level 0?
Level 1
No
Yes
No

Related parts for HD64F7047F50V