HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 37

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Section 3 MCU Operating Modes
Table 3.1
Table 3.2
Table 3.3
Section 4 Clock Pulse Generator
Table 4.1
Table 4.2
Section 5 Exception Processing
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Table 5.9
Table 5.10
Table 5.11
Section 6 Interrupt Controller (INTC)
Table 6.1
Table 6.2
Table 6.3
Section 8 Data Transfer Controller (DTC)
Table 8.1
Table 8.2
Initial Values of Registers....................................................................................... 17
Sign Extension of Word Data ................................................................................. 20
Delayed Branch Instructions................................................................................... 20
T Bit ........................................................................................................................ 21
Immediate Data Accessing ..................................................................................... 21
Absolute Address Accessing................................................................................... 22
Displacement Accessing ......................................................................................... 22
Addressing Modes and Effective Addresses........................................................... 23
Instruction Formats ................................................................................................. 27
Classification of Instructions .................................................................................. 29
Selection of Operating Modes ................................................................................ 45
Maximum Operating Clock Frequency for Each Clock Mode ............................... 46
Operating Mode Pin Configuration......................................................................... 46
Damping Resistance Values ................................................................................... 52
Crystal Resonator Characteristics ........................................................................... 52
Types of Exception Processing and Priority ........................................................... 57
Timing for Exception Source Detection and Start of Exception Processing........... 58
Exception Processing Vector Table ........................................................................ 59
Calculating Exception Processing Vector Table Addresses.................................... 60
Reset Status............................................................................................................. 61
Bus Cycles and Address Errors............................................................................... 63
Interrupt Sources..................................................................................................... 65
Interrupt Priority ..................................................................................................... 66
Types of Exceptions Triggered by Instructions ...................................................... 67
Generation of Exception Sources Immediately after a Delayed Branch
Instruction or Interrupt-Disabled Instruction .......................................................... 69
Stack Status after Exception Processing Ends ........................................................ 70
Pin Configuration.................................................................................................... 75
Interrupt Exception Processing Vectors and Priorities ........................................... 85
Interrupt Response Time......................................................................................... 91
Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs ................. 120
Normal Mode Register Functions ......................................................................... 123
Tables
Rev. 2.00, 09/04, page xxxv of xl