HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 293

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match
signal is not generated until the TCNT input clock is generated.
Figure 10.57 shows output compare output timing (normal mode and PWM mode) and Figure
10.58 shows output compare output timing (complementary PWM mode and reset synchronous
PWM mode).
External
clock
TCNT input
clock
Pφ
TCNT
Figure 10.56 Count Timing in External Clock Operation (Phase Counting Mode)
TCNT input
clock
TCNT
TGR
Compare
match signal
TIOC pin
Pφ
Figure 10.57 Output Compare Output Timing (Normal Mode/PWM Mode)
Falling edge
N
N
N-1
Rising edge
N+1
N
Rev. 2.00, 09/04, page 251 of 720
Falling edge
N+1