HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 62

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.4
2.4.1
All instructions are RISC type. This section details their functions.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
One Instruction per State: The microprocessor can execute basic instructions in one state using
the pipeline system. One state is 25 ns at 40 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations. It also is handled as longword data.
Table 2.2
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions.
With a delayed branch instruction, the branch is taken after execution of the instruction following
the delayed branch instruction. This reduces the disturbance of the pipeline control in case of
branch instructions. There are two types of conditional branch instructions: delayed branch
instructions and ordinary branch instructions.
Table 2.3
Rev. 2.00, 09/04, page 20 of 720
CPU of This LSI
MOV.W
ADD
.DATA.W
CPU of This LSI
BRA
ADD
Instruction Features
RISC-Type Instruction Set
TRGET
R1,R0
@(disp,PC),R1
R1,R0
.........
H'1234
Sign Extension of Word Data
Delayed Branch Instructions
Description
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
Description
Executes the ADD before
branching to TRGET.
Example of Conventional CPU
ADD.W
Example of Conventional CPU
ADD.W
BRA
#H'1234,R0
R1,R0
TRGET