HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 353

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
Output Level Control/Status Register (OCSR): The output level control/status register (OCSR)
is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins
become high impedance.
Bit
1
0
Bit
15
14 to 10 
*
Bit Name
POE0M1
POE0M0
Bit Name
OSF
The write value should always be 0.
Initial
value
0
0
0
Initial
value
All 0
R/W
R/W
R/W
R/W
R/(W)* Output Short Flag
R
Description
POE0 mode 1, 0
These bits select the input mode of the POE0 pin
00: Accept request on falling edge of POE0 input
01: Accept request when POE0 input has been sampled
10: Accept request when POE0 input has been sampled
11: Accept request when POE0 input has been sampled
Description
This flag indicates that any one pair of the three pairs of 2
phase outputs compared have simultaneously become
low level outputs.
[Clear condition]
•
[Set condition]
•
Reserved
These bits are always read as 0. These bits should
always be written with 0
for 16 Pφ/8 clock pulses, and all are low level.
for 16 Pφ/16 clock pulses, and all are low level.
for 16 Pφ/128 clock pulses, and all are low level.
By writing 0 to OSF after reading an OSF = 1
When any one pair of the three 2-phase outputs
simultaneously become low level
Rev. 2.00, 09/04, page 311 of 720