HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 652

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

MSTCR2
Note:
Rev. 2.00, 09/04, page 610 of 720
Bit
15
14
13
12
11
10
9
8
7, 6
5
4
3
2
1
0
Bit Name



MSTP9


MSTP5
MSTP4
MSTP3
MSTP2

MSTP0
MSTP14
MSTP13
MSTP12
*
In E10A debugging mode (when DBGMD = low-level input), although this bit can be
read and written, AUD and H-UDI are always operated regardless of set values.
Initial
Value
1
1
1
1
0
0
0
0
All 1
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Description
Reserved
This bit is always read as 1, and should always be
written with 1.
Motor management timer (MMT)
Multi-function timer pulse unit (MTU)
Compare match timer (CMT)
Reserved
These bits are always read as 0, and should always be
written with 0.
Renesas controller area network 2 (HCAN2)
Reserved
This bit is always read as 0, and should always be
written with 0.
Reserved
This bit is always read as 1, and should always be
written with 1.
A/D converter (A/D1)
A/D converter (A/D0)
Advanced user debugger (AUD)*
Renesas user debug interface (H-UDI)*
Reserved
This bit is always read as 0, and should always be
written with 0.
User break controller (UBC)