HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 579

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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This LSI has five ports: A, B, D, E, and F. Port A is a 16-bit port, port B is a 6-bit port, port D is a
9-bit port, and port E is a 22-bit port, all supporting both input and output. Port F is a 16-bit input-
only port.
All the port pins are multiplexed as general input/output pins and special function pins. The
functions of the multiplex pins are selected by means of the pin function controller (PFC). Each
port is provided with a data register for storing the pin data.
18.1
Port A is an input/output port with the 16 pins shown in figure 18.1.
Note: * Only for the F-ZTAT version (no corresponding function in the mask version.)
Port A
Port A
PA15 (I/O) / CK (output) / POE6 (input) / TRST (input)* / BACK (output)
PA14 (I/O) / RD (output) / POE5 (input) / TMS (input)*
PA13 (I/O) / POE4 (input) / TDO (output)* /BREQ (input)
PA12 (I/O) / WRL (output) / UBCTRG (output)* / TDI (input)*
PA11 (I/O) / ADTRG (input) / SCK3 (I/O)
PA10 (I/O) / CS0 (output) / RD (output) / TCK (input)* / SCK2 (I/O)
PA9 (I/O) / TCLKD (input) / IRQ3 (input) / TXD3 (output)
PA8 (I/O) / TCLKC (input) / IRQ2 (input) / RXD3 (input)
PA7 (I/O) / TCLKB (input) / WAIT (input) / TXD2 (output)
PA6 (I/O) / TCLKA (input) / RD (output) / RXD2 (input)
PA5 (I/O) / IRQ1 (input) / A5 (output) / POE6 (input) / SCK3 (I/O)
PA4 (I/O) / A4 (output) / POE5 (input) / TXD3 (output)
PA3 (I/O) / A3 (output) / POE4 (input) / RXD3 (input)
PA2 (I/O) / IRQ0 (input) / A2 (output) / PCIO (I/O) / SCK2 (I/O)
PA1 (I/O) / A1 (output) / POE1 (input) / TXD2 (output)
PA0 (I/O) / A0 (output) / POE0 (input) / RXD2 (input)
Section 18 I/O Ports
Figure 18.1 Port A
Rev. 2.00, 09/04, page 537 of 720

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