HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 542

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Requests to start A/D conversion is enabled by setting the bit TTGE in the timer control register
(TCNR) to 1.
Table 16.3 shows the relationship between A/D conversion start timing and operating mode.
Table 16.3 Relationship between A/D Conversion Start Timing and Operating Mode
16.4.2
Operating mode output has the following protection functions:
• Halting MMT output by external signal
• Halting MMT output when oscillation stops
16.5
When the TGFM (TGFN) flag is set to 1 in the timer status register (TSR) by a compare match
between TCNT and the TPDR register (2Td), and if the TGIEM (TGIEN) bit setting in the timer
control register (TCNR) is 1, an interrupt is requested. The interrupt request is cleared by clearing
the TGF flag to 0.
Table 16.4 MMT Interrupt Sources
The on-chip DTC can be activated by a compare match between TCNT and TPDR or between
TCNT and 2Td.
Rev. 2.00, 09/04, page 500 of 720
Operating mode
Operating mode 1 (transfer at peak)
Operating mode 2 (transfer at bottom)
Operating mode 3 (transfer at peak and bottom) A/D conversion start at peak and bottom
Name
TGIMN
TGINN
The 6-phase PWM output pins can be placed in the high-impedance state automatically by
inputting a specified external signal. There are three external signal input pins. For details, see
section 16.8, Port Output Enable (POE).
The 6-phase PWM output pins are placed in the high-impedance state automatically when
stoppage of the clock input is detected. However, pin states are not guaranteed when the clock
is restarted.
Output Protection Functions
Interrupts
Interrupt Source
Compare match between TCNT and TPDR
Compare match between TCNT and 2Td
A/D conversion start timing
A/D conversion start at bottom
A/D conversion start at peak
Interrupt Flag
TGFM
TGFN
DTC Activation
Yes
Yes