HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 369

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other
registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for TCSR,
H'FFFF8611 for TCNT, and H'FFFF8613 for RSTCSR.
11.6.2
If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT,
the write takes priority and the timer counter is not incremented. Figure 11.8 shows this operation.
11.6.3
If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while
the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by
clearing the TME bit to 0) before rewriting the values of bits CKS2 to CKS0.
11.6.4
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
TCNT Write and Increment Contention
Changing CKS2 to CKS0 Bit Values
Changing between Watchdog Timer/Interval Timer Modes
Address
Internal write
signal
TCNT input
clock
TCNT
Figure 11.8 Contention between TCNT Write and Increment
φ
TCNT write cycle
T 1
TCNT address
N
T 2
Counter write data
T 3
Rev. 2.00, 09/04, page 327 of 720
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