HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 414

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6.4
Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
Rev. 2.00, 09/04, page 372 of 720
Synchroniza-
tion clock
Serial data
RDRF
ORER
or output, starts receiving data, and stores the received data in RSR.
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt processing routine reads the receive data transferred to
RDR before reception of the next receive data has finished, continuous reception can be
enabled.
Serial data reception (Clocked Synchronous mode)
RXI interrupt
request
generated
Figure 12.18 Example of SCI Operation in Reception
Bit 7
Bit 0
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
1 frame
Bit 7
Bit 0
RXI interrupt
request
generated
Bit 1
Bit 6
ERI interrupt
request generated
by overrun error
Bit 7