HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 536

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Register Operation: In the operating modes, four buffer registers and ten compare registers are
used.
The registers that are constantly compared with the TCNT counter are TGRU, TGRV, and
TGRW. In addition, TGRUU, TGRVU, TGRWU, and TPDR are compared with TCNT when
TCNT is counting up, and TGRUD, TGRVD, TGRWD are compared with TCNT when TCNT is
counting down. The buffer register for TPDR is TPBR; the buffer register for TGRUU, TGRU,
and TGRUD is TBRU; the buffer register for TGRVU, TGRV, and TGRVD is TBRV; and the
buffer register for TGRWU, TGRW, and TGRWD is TBRW.
To change compare register data, the new data should be written to the corresponding buffer
register. The buffer registers can be read and written to at all times. Data written to the buffer
operation addresses for TPBR and TBRU to TBRW is transferred at the timing specified by bits
MD1 and MD0 in the timer mode register (TMDR). Data written to the free operation addresses
for TBRU to TBRW is transferred immediately.
After data transfer is completed, the relationship between the compare registers and buffer
registers is as follows:
TGRU (TGRV, TGRW) value = TBRU (TBRV, TBRW) value + Td (Td: value set in TDDR)
TGRUU (TGRVU, TGRWU) value = TBRU (TBRV, TBRW) value + 2Td
TGRUD (TGRVD, TGRWD) value = TBRU (TBRV, TBRW) value
TPDR value = TPBR value + 2Td
The values of TBRU to TBRW should always be set in the range H'0000 to H'FFFF – 2Td, and the
value of TPBR should always be set in the range H'0000 to H'FFFF – 4Td.
Figure 16.4 shows examples of counter and register operations.
Rev. 2.00, 09/04, page 494 of 720