HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 505

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit
configuration register (BCR). Settings should be made such that all CAN controllers connected to
the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the
settable time quanta (TQ). Figure 15.7 shows details of the 1-bit time.
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is performed. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is performed. Limits on the BCR settable values (TSEG1, TSEG2, BRP,
sample point, and SJW) are shown in table 15.4.
Table 15.4 Limits on BCR Settable Values
Notes: 1. SJW is stipulated in the CAN specifications:
Name
Time segment 1
Time segment 2
Baud rate prescaler
Bit sample point
Re-synchronization jump width
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
4 ≥ SJW ≥ 1
TSEG2 ≥ SJW
TSEG1 > TSEG2
Stipulated as: TSEG1 + TSEG2 + 1 = 8 to 25 TQ (Time Quanta)
1 time quanta
SYNC_SEG
Figure 15.7 Detailed Description of 1-Bit Time
1-bit time (8 to 25 time quanta)
PRSEG
Time segment 1 (TSEG1)
4 to 16 time quanta
TSEG1
TSEG2
BRP
BSP
SJW*
Abbreviation
1
PHSEG1
Min. Value
4*
2*
1
1
1
3
2
Rev. 2.00, 09/04, page 463 of 720
2 to 8 time quanta
Time segment 2
(TSEG2)
PHSEG2
Max. Value
16
8
256
3
4