DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 938

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 23 List of Registers
Note:
Rev.1.00 Sep. 08, 2005 Page 888 of 966
REJ09B0219-0100
Register Name
Timer control register_1
Timer mode register_1
Timer I/O control register_1
Timer interrupt enable register_1
Timer status register_1
Timer counter_1
Timer general register A_1
Timer general register B_1
Timer control register_2
Timer mode register_2
Timer I/O control register_2
Timer interrupt enable register_2
Timer status register_2
Timer counter_2
Timer general register A_2
Timer general register B_2
Timer control register_3
Timer mode register_3
Timer I/O control register H_3
Timer I/O control register L_3
Timer interrupt enable register_3
Timer status register_3
Timer counter_3
Timer general register A_3
Timer general register B_3
Timer general register C_3
Timer general register D_3
*
When the same output trigger is specified for pulse output groups 2 and 3 by the PCR
setting, the NDRH address is H'FFF7C. When different output triggers are specified, the
NDRH addresses for pulse output groups 2 and 3 are H'FFF7E and H'FFF7C,
respectively. Similarly, When the same output trigger is specified for pulse output
groups 0 and 1 by the PCR setting, the NDRL address is H'FFF7D. When different
output triggers are specified, the NDRL addresses for pulse output groups 0 and 1 are
H'FFF7F and H'FFF7D, respectively.
Abbreviation
TCR_1
TMDR_1
TIOR_1
TIER_1
TSR_1
TCNT_1
TGRA_1
TGRB_1
TCR_2
TMDR_2
TIOR_2
TIER_2
TSR_2
TCNT_2
TGRA_2
TGRB_2
TCR_3
TMDR_3
TIORH_3
TIORL_3
TIER_3
TSR_3
TCNT_3
TGRA_3
TGRB_3
TGRC_3
TGRD_3
8
16
16
8
16
16
8
8
16
16
Number
of Bits
8
8
8
8
16
8
8
8
8
16
8
8
8
8
16
16
16
Address
H'FFFD0
H'FFFD2
H'FFFD4
H'FFFD8
H'FFFDA
H'FFFE2
H'FFFE4
H'FFFE5
H'FFFE8
H'FFFEA
H'FFFF0
H'FFFF2
H'FFFF3
H'FFFF4
H'FFFF8
H'FFFFA
H'FFFD1
H'FFFD5
H'FFFD6
H'FFFE0
H'FFFE1
H'FFFE6
H'FFFF1
H'FFFF5
H'FFFF6
H'FFFFC
H'FFFFE
Module
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
TPU_3
Data
Width
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Access
Cycles
(Read/Write)
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ