DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 538

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 Programmable Pulse Generator (PPG)
11.4
Figure 11.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values. Sequential
output of data of up to eight bits is possible by writing new output data to NDR before the next
compare match.
Rev.1.00 Sep. 08, 2005 Page 488 of 966
REJ09B0219-0100
Bit
0
Bit Name
G0NOV
Operation
Pulse output pin
0
Initial
Value
Figure 11.2 Schematic Diagram of PPG
R/W
R/W
Normal output/inverted output
Description
Group 0 Non-Overlap
Selects normal or non-overlapping operation for pulse
output group 0.
0: Normal operation (output values updated at compare
1: Non-overlapping operation (output values updated at
match A in the selected TPU channel)
compare match A or B in the selected TPU channel)
Q
NDER
PODR
Q
C
Output trigger signal
D
Q
NDR
D
Internal data bus