DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 684

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface (SCI, IrDA, CRC)
(2)
CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written.
The result is obtained in CRCDOR.
(3)
CRCDOR is a 16-bit readable/writable register that contains the result of CRC operation when the
bytes to be CRC-operated are written to CRCDIR after CRCDOR is cleared. When the CRC
operation result is additionally written to the bytes to which CRC operation is to be performed, the
CRC operation result will be H'0000 if the data contains no CRC error. When bits 1 and 0 in
CRCCR (G1 and G0 bits) are set to 0 and 1, respectively, the lower byte of this register contains
the result.
Rev.1.00 Sep. 08, 2005 Page 634 of 966
REJ09B0219-0100
Bit
1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
CRC Data Input Register (CRCDIR)
CRC Data Output Register (CRCDOR)
Bit Name
G1
G0
R/W
R/W
R/W
7
0
7
0
7
0
Initial
Value
0
0
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
R/W
R/W
R/W
5
0
5
0
5
0
Description
CRC Generating Polynomial Select:
Selects the polynomial.
00: Reserved
01: X
10: X
11: X
R/W
R/W
R/W
8
16
16
4
0
4
0
4
0
+ X
+ X
+ X
2
15
12
+ X + 1
+ X
+ X
R/W
R/W
R/W
2
5
3
0
3
0
3
0
+ 1
+ 1
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0