DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 265

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6)
Depending on the system's load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 6.44. In this case, with the setting for no idle cycle insertion (a), there
may be a period of overlap between the RD signal in bus cycle A and the CS signal in bus cycle B.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals. In the initial state after reset release, idle cycle indicated in (b) is set.
B
Address bus
CS (area A)
CS (area B)
RD
Relationship between Chip Select (CS) Signal and Read (RD) Signal
Figure 6.42 Relationship between Chip Select (CS) and Read (RD)
(a) No idle cycle inserted
Overlap time may occur between the
CS (area B) and RD
T
Bus cycle A
1
(IDLS1 = 0)
T
2
T
3
Bus cycle B
T
1
T
2
(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Rev.1.00 Sep. 08, 2005 Page 215 of 966
T
Bus cycle A
1
(b) Idle cycle inserted
T
2
Section 6 Bus Controller (BSC)
T
3
T
i
Bus cycle B
REJ09B0219-0100
T
1
T
2