DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 151

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.3.6
ISR is an IRQ11 to IRQ0 interrupt request register.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: *
Note:
Bit
15 to 12
11
10
9
8
7
6
5
4
3
2
1
0
*
Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should
be used to clear the flag.
IRQ Status Register (ISR)
Bit Name

IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Only 0 can be written, to clear the flag.
R/(W)*
IRQ7F
R/W
15
0
7
0
R/(W)*
IRQ6F
Initial
Value
All 0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
14
0
6
0
R/W
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRQ5F
R/W
13
0
5
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
[Setting condition]
•
[Clearing conditions]
•
•
•
•
R/(W)*
IRQ4F
R/W
12
0
4
0
When the interrupt selected by ISCR occurs
Writing 0 after reading IRQnF = 1
When interrupt exception handling is executed when
low-level sensing is selected and IRQn input is high
When IRQn interrupt exception handling is executed
when falling-, rising-, or both-edge sensing is
selected
When the DTC is activated by an IRQn interrupt,
and the DISEL bit in MRB of the DTC is cleared to 0
IRQ11F
R/(W)*
R/(W)*
IRQ3F
11
0
3
0
Rev.1.00 Sep. 08, 2005 Page 101 of 966
IRQ10F
R/(W)*
R/(W)*
IRQ2F
10
0
2
0
Section 5 Interrupt Controller
R/(W)*
R/(W)*
IRQ9F
IRQ1F
9
0
1
0
REJ09B0219-0100
R/(W)*
R/(W)*
IRQ0F
IRQ8F
8
0
0
0