DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 561

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes: 1. To use an external reset or external clock, the DDR and ICR bits in the corresponding
Bit
6
5
4
3
2
1
0
2. In unit 2 and unit 3, one interrupt signal is used for CMIEB or CMIEA. For details, see
3. Available only in unit 0 and unit 1
Bit Name
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
pin should be set to 0 and 1, respectively. For details, see section 9, I/O Ports.
12.7, Interrupt Sources.
Initial
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests (CMIA) are
enabled or disabled when the CMFA flag in TCSR is set
to 1. *
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
Timer Overflow Interrupt Enable*
Selects whether OVF interrupt requests (OVI) are
enabled or disabled when the OVF flag in TCSR is set to
1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
Counter Clear 1 and 0*
These bits select the method by which TCNT is cleared.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared at rising edge (TMRIS in TCCR is cleared to
Clock Select 2 to 0*
These bits select the clock input to TCNT and count
condition. See table 12.2.
0) of the external reset input or when the external
reset input is high (TMRIS in TCCR is set to 1) *
2
1
Rev.1.00 Sep. 08, 2005 Page 511 of 966
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Section 12 8-Bit Timers (TMR)
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REJ09B0219-0100
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