DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 900

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 21 Clock Pulse Generator
21.3
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 4. The frequency multiplication rate is fixed. The phase difference is controlled so that
the timing of the rising edge of the internal clock is the same as that of the EXTAL pin signal.
21.4
The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After the bits
ICK2 to ICK0, PCK 2 to PCK0, and BCK2 to BCK0 are updated, this LSI operates with the
updated frequency.
21.5
21.5.1
1. The following points should be noted since the frequency of φ (Iφ: system clock, Pφ:
2. All the on-chip peripheral modules (except for the DMAC and DTC) operate on the Pφ. Note
3. The relationship among the system clock, peripheral module clock, and external bus clock is Iφ
4. Note that the frequency of φ will be changed in the middle of a bus cycle when setting SCKCR
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peripheral module clock, Bφ: external bus clock) supplied to each module changes according
to the setting of SCKCR.
Select a clock division ratio that is within the operation guaranteed range of clock cycle time
t
The frequency should be set under the conditions of 8 MHz ≤ Iφ ≤ 50 MHz, 8 MHz ≤ Pφ ≤ 35
MHz, and 8 MHz ≤ Bφ ≤ 50 MHz.
therefore that the time processing of modules such as a timer and SCI differs before and after
changing the clock division ratio.
In addition, wait time for clearing software standby mode differs by changing the clock
division ratio. For details, see section 22.5.3, Setting Oscillation Settling Time after Clearing
Software Standby Mode.
≥ Pφ and Iφ ≥ Bφ. In addition, the system clock setting has the highest priority. Accordingly,
Pφ or Bφ may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits
PCK2 to PCK0 or BCK2 to BCK0.
while executing the external bus cycle with the write-data-buffer function.
cyc
shown in the AC timing of electrical characteristics.
PLL Circuit
Frequency Divider
Usage Notes
Notes on Clock Pulse Generator