DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 566

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 8-Bit Timers (TMR)
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.1.00 Sep. 08, 2005 Page 516 of 966
REJ09B0219-0100
Bit
5
4
3
2
1
0
2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first
3. Available in unit 0 and unit 1 only.
Bit Name
OVF
ADTE
OS3
OS2
OS1
OS0
compare match occurs after a reset.
Initial
Value
0
0
0
0
0
0
R/W
R/(W)*
R/W
R/W
R/W
R/W
R/W
1
Description
Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FF to H'00
[Clearing condition]
When writing 0 after reading OVF = 1
A/D Trigger Enable*
Selects enabling or disabling of A/D converter start
requests by compare match A.
0: A/D converter start requests by compare match A are
1: A/D converter start requests by compare match A are
Output Select 3 and 2*
These bits select a method of TMO pin output when
compare match B of TCORB and TCNT occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B occurs
Output Select 1 and 0*
These bits select a method of TMO pin output when
compare match A of TCORA and TCNT occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A occurs
disabled
enabled
(toggle output)
(toggle output)
3
2
2