DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 773

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4.4
In slave transmit mode, the slave device outputs the transmit data, and the master device outputs
the receive clock pulse and returns an acknowledge signal. Figures 16.9 and 16.10 show the
operation timings in slave transmit mode. The transmission procedure and operations in slave
transmit mode are described below.
1. Set the ICR bit in the corresponding register to 1, then set the ICE bit in ICCRA to 1. Set the
2. When the slave address matches in the first frame following the detection of the start
3. If TDRE is set after writing the last transmit data to ICDRT, wait until TEND in ICSR is set to
4. Clear TRS for end processing, and read ICDRR (dummy read) to free SCL.
5. Clear TDRE.
(Master output)
(Master output)
(Slave output)
ACKBIT in ICIER, and perform other initial settings. Set the MST and TRS bits in ICCRA to
select slave receive mode, and wait until the slave address matches.
condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the
rising of the ninth clock pulse. At this time, if the eighth bit data (R/W) is 1, TRS in ICCRA
and TDRE in ICSR are set to 1, and the mode changes to slave transmit mode automatically.
The continuous transmission is performed by writing the transmit data to ICDRT every time
TDRE is set.
1, with TDRE = 1. When TEND is set, clear TEND.
processing
ICDRR
ICDRS
RDRF
RCVD
User
SDA
SDA
SCL
Slave Transmit Operation
Data n-1
[5] Set RCVD then read ICDRR
Figure 16.8 Master Receive Mode Operation Timing 2
A
9
Data n-1
Bit 7
1
Bit 6
2
Bit 5
3
[6] Issue stop condition [7] Read ICDRR and clear RCVD
Bit 4
4
Bit 3
5
Bit 2
6
Rev.1.00 Sep. 08, 2005 Page 723 of 966
Bit 1
7
Section 16 I
Data n
Bit 0
8
A/A
9
[8] Set slave receive mode
Data n
2
C Bus Interface2 (IIC2)
REJ09B0219-0100