DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 24

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.4 Interrupt Sources................................................................................................................ 672
15.5 Operation ........................................................................................................................... 674
15.6 Processing of USB Standard Commands and Class/Vendor Commands .......................... 691
15.7 Stall Operations.................................................................................................................. 692
15.8 DMA Transfer.................................................................................................................... 695
15.9 Example of USB External Circuitry .................................................................................. 697
15.10 Usage Notes ....................................................................................................................... 699
Section 16 I
16.1 Features.............................................................................................................................. 703
16.2 Input/Output Pins............................................................................................................... 705
16.3 Register Descriptions......................................................................................................... 706
Rev.1.00 Sep. 08, 2005 Page xxii of xlviii
15.3.21 DMA Transfer Setting Register (DMA) ............................................................... 658
15.3.22 Endpoint Stall Register (EPSTL).......................................................................... 661
15.3.23 Configuration Value Register (CVR) ................................................................... 662
15.3.24 Control Register (CTLR) ...................................................................................... 662
15.3.25 Endpoint Information Register (EPIR) ................................................................. 664
15.3.26 Transceiver Test Register 0 (TRNTREG0) .......................................................... 668
15.3.27 Transceiver Test Register 1 (TRNTREG1) .......................................................... 670
15.5.1 Cable Connection.................................................................................................. 674
15.5.2 Cable Disconnection ............................................................................................. 675
15.5.3 Suspend and Resume Operations.......................................................................... 676
15.5.4 Control Transfer.................................................................................................... 681
15.5.5 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................... 687
15.5.6 EP2 Bulk-In Transfer (Dual FIFOs) ..................................................................... 688
15.5.7 EP3 Interrupt-In Transfer...................................................................................... 690
15.6.1 Processing of Commands Transmitted by Control Transfer................................. 691
15.7.1 Overview .............................................................................................................. 692
15.7.2 Forcible Stall by Application ................................................................................ 692
15.7.3 Automatic Stall by USB Function Module ........................................................... 694
15.8.1 Overview .............................................................................................................. 695
15.8.2 DMA Transfer for Endpoint 1 .............................................................................. 695
15.8.3 DMA Transfer for Endpoint 2 .............................................................................. 696
15.10.1 Receiving Setup Data ........................................................................................... 699
15.10.2 Clearing the FIFO ................................................................................................. 699
15.10.3 Overreading and Overwriting the Data Registers ................................................. 699
15.10.4 Assigning Interrupt Sources to EP0...................................................................... 700
15.10.5 Clearing the FIFO When DMA Transfer is Enabled ............................................ 700
15.10.6 Notes on TR Interrupt ........................................................................................... 700
15.10.7 Restrictions on Peripheral Module Clock (Pφ) Operating Frequency................... 701
2
C Bus Interface2 (IIC2)................................................................. 703