DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 711

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.3.22 Endpoint Stall Register (EPSTL)
The bits in EPSTL are used to forcibly stall the endpoints on the application side. While a bit is set
to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0
is cleared automatically on reception of 8-byte command data for which decoding is performed by
the function and the EP0 STL bit is cleared. When the SETUPTS flag in the IFR0 register is set to
1, writing 1 to the EP0 STL bit is ignored. For detailed operation, see section 15.7, Stall
Operations.
Bit
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name
EP3STL
EP2STL
EP1STL
EP0STL
R
7
0
Initial
Value
0
0
0
0
0
0
0
0
R
6
0
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R
5
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
EP3 Stall
When this bit is set to 1, endpoint 3 is placed in the
stall state.
EP2 Stall
When this bit is set to 1, endpoint 2 is placed in the
stall state.
EP1 Stall
When this bit is set to 1, endpoint 1 is placed in the
stall state.
EP0 Stall
When this bit is set to 1, endpoint 0 is placed in the
stall state.
R
4
0
EP3STL
R/W
3
0
Rev.1.00 Sep. 08, 2005 Page 661 of 966
Section 15 USB Function Module (USB)
EP2STL
R/W
2
0
EP1STL
R/W
1
0
REJ09B0219-0100
EP0STL
R/W
0
0

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