DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 244

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
6.8.3
Table 6.17 shows the pins used for the burst ROM interface.
Table 6.17 I/O Pins Used for Burst ROM Interface
Rev.1.00 Sep. 08, 2005 Page 194 of 966
REJ09B0219-0100
Name
Bus cycle start
Address strobe
Read strobe
Read/write
Low-high write
Low-low write
Chip select 0 to 7
Wait
I/O Pins Used for Burst ROM Interface
Symbol
BS
AS
RD
RD/WR
LHWR
LLWR
CS0 to CS7 Output
WAIT
I/O
Output
Output
Output
Output
Output
Output
Input
Function
Signal indicating that the bus cycle has
started.
Strobe signal indicating that an address output on
the address bus is valid during access
Strobe signal indicating the read access
Signal indicating the data bus input or output
direction
Strobe signal indicating that the upper byte (D15 to
D8) is valid during write access
Strobe signal indicating that the lower byte (D7 to
D0) is valid during write access
Strobe signal indicating that the area is selected
Wait request signal used when an external address
space is accessed

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