DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 245

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8.4
The number of access cycles in the initial cycle (full access) on the burst ROM interface is
determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits
CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space is read by
the CPU, the settings in RDNCR and bits CSXTn in CSACR (n = 0 to 7) are ignored.
From one to eight cycles can be selected for the burst cycle, according to the settings of bits
BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait cycles cannot be inserted. In
addition, 4-word, 8-word, 16-word, or 32-word consecutive burst access can be performed
according to the settings of BSTS01, BSTS00, BSTS11, and BSTS10 bits in BROMCR.
The basic access timing for burst ROM space is shown in figures 6.28 and 6.29.
B
Upper
Lower
address bus
CSn
AS
RD
Data bus
BS
RD/WR
address bus
Figure 6.28 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)
Note: n = 1, 0
Basic Timing
T
1
Full access
T
2
T
3
T
1
Rev.1.00 Sep. 08, 2005 Page 195 of 966
T
Burst access
2
Section 6 Bus Controller (BSC)
T
1
REJ09B0219-0100
T
2