DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 167

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1)
The activation source for each DMAC channel is selected by DMRSR. The selected activation
source is input to the DMAC through the select circuit. When transfer by an on-chip module
interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is
set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC
and cannot be used as a DTC activation source or CPU interrupt source.
Interrupt sources that are not controlled by the DMAC are set for DTC activation sources or CPU
interrupt sources by the DTCE bit in DTCERA to DTCERH of the DTC.
Specifying the DISEL bit in MRB of the DTC generates an interrupt request to the CPU by
clearing the DTCE bit to 0 after the individual DTC data transfer.
Note that when the DTC performs a predetermined number of data transfers and the transfer
counter indicates 0, an interrupt request is made to the CPU by clearing the DTCE bit to 0 after the
DTC data transfer.
When the same interrupt source is set as both the DTC and DMAC activation source and CPU
interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in
CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP
setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal
to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or
DMAC may not be activated, and the data transfer may not be performed.
Selection of Interrupt Sources
peripheral
On-chip
interrupt
module
IRQ
Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller
Interrupt request
Interrupt request
Interrupt request clear signal
Interrupt request
clear signal
Interrupt controller
DMAC
select
circuit
Interrupt request
Select signal
Clear signal
DTC/CPU
DMRSR_0 to DMRSR_3
DTCER
select
circuit
Select signal
Clear signal
DMAC activation request signal
Rev.1.00 Sep. 08, 2005 Page 117 of 966
Control signal
determination
Clear signal
DTC control
Priority
circuit
Section 5 Interrupt Controller
CPU interrupt request
DTC activation request
vector number
vector number
Clear signal
I, I2 to I0
REJ09B0219-0100
DMAC
DTC
CPU