DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 855

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The procedure program must be executed in an area other than the user MAT to be erased. Setting
the SCO bit in FCCS to 1 to request download must be executed in the on-chip RAM. The area
that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external
space) is shown in section 20.7.4, On-Chip Program and Storable Area for Program Data. For the
downloaded on-chip program area, see figure 20.12.
One erasure processing erases one block. For details on block divisions, refer to figures 20.3 and
20.4. To erase two or more blocks, update the erase block number and repeat the erasing
processing for each block.
1. Select the on-chip program to be downloaded and the download destination. When the PPVS
4. The return value in the erasing program, the FPFR parameter is determined.
5. Determine whether erasure of the necessary blocks has finished. If more than one block is to
6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by
2. Set the FEBS parameter necessary for erasure. Set the erase block number (FEBS parameter)
3. Erasure is executed. Similar to as in programming, the entry point of the erasing program is at
bit in FPCS is set to 1, the programming program is selected. Several programming/erasing
programs cannot be selected at one time. If several programs are selected, a download error is
returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download
destination is specified by FTDAR.
For the procedures to be carried out after setting FKEY, see section 20.7.3 (2), Programming
Procedure in User Program Mode.
of the user MAT in general register ER0. If a value other than an erase block number of the
user MAT is set, no block is erased even though the erasing program is executed, and an error
is returned to the FPFR parameter.
the address which is 16 bytes after #DLTOP (start address of the download destination
specified by FTDAR). Call the subroutine to execute erasure by using the following steps.
MOV.L #DLTOP+16, ER2
JSR
NOP
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be erased, update the FEBS parameter and repeat steps 2 to 5.
a power-on reset immediately after erasure has finished, secure the reset input period (period
of RES = 0) of at least 100 µs.
The general registers other than ER0 or ER1 are held in the erasing program.
R0L is a return value of the FPFR parameter.
Since the stack area is used in the erasing program, a stack area of 128 bytes at the
maximum must be allocated in RAM.
@ER2
; Set entry address to ER2
; Call erasing routine
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
Rev.1.00 Sep. 08, 2005 Page 805 of 966
REJ09B0219-0100