DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 310

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
(2)
In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up
to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in
DBSR up to 65536 × data access size.
The repeat area can be specified for the source or destination address side by bits ARS1 and ARS0
in DACR. The address specified as the repeat area returns to the transfer start address when the
repeat size of transfers is completed. This operation is repeated until the total transfer size
specified in DTCR is completed. When H'00000000 is specified in DTCR, it is regarded as the
free running mode and repeat transfer is continued until the DTE bit in DMDR is cleared to 0.
In addition, a DMA transfer can be stopped and a repeat size end interrupt can be requested to the
CPU or DTC when the repeat size of transfers is completed. When the next transfer is requested
after completion of a 1-repeat size data transfer while the RPTIE bit is set to 1, the DTE bit in
DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1 to complete the transfer. At this time,
an interrupt is requested to the CPU or DTC when the ESIE bit in DMDR is set to 1.
The timings of the TEND and DACK signals are the same as in normal transfer mode.
Figure 7.9 shows the operation in repeat transfer mode while dual address mode is set.
When the repeat area is specified as neither source nor destination address side, the operation is
the same as the normal transfer mode operation shown in figure 7.8. In this case, a repeat size end
interrupt can also be requested to the CPU when the repeat size of transfers is completed.
Rev.1.00 Sep. 08, 2005 Page 260 of 966
REJ09B0219-0100
Address B
Address T
Repeat Transfer Mode
A
A
Figure 7.8 Operations in Normal Transfer Mode
Total transfer
size (DTCR)
Transfer
Address T
Address B
B
B